Logic Analyser
For my Master’s thesis at EPFL, I implemented a System-on-Chip (SoC) for an FPGA in Verilog, centred around the Hazard3 RISC-V processor. The system is designed as an educational platform that enables EPFL students to gain practical experience in both software development and hardware design for embedded systems. The platform targets the Gecko5Education board, developed […]
