Vectorized Text Rendering
As part of my goal to write a custom GUI library for my own projects, I had to find a way to render text. There are different ways this can be done. Probably the most commonly used technique is to pre-render all glyphs in different sizes to so-called font atlases. When rendering text, the required […]
Logic Analyser
For my Master’s thesis at EPFL, I implemented a System-on-Chip (SoC) for an FPGA in Verilog, centred around the Hazard3 RISC-V processor. The system is designed as an educational platform that enables EPFL students to gain practical experience in both software development and hardware design for embedded systems. The platform targets the Gecko5Education board, developed […]
